DRV8306HRSMR

1 Features

• Triple Half-Bridge Gate Driver

– Drives High-Side and Low-Side N-Channel MOSFETs

– Supports 100% PWM Duty Cycle

• Smart Gate Drive Architecture

– Adjustable Slew-Rate Control

– 15-mA to 150-mA Peak Source Current

– 30-mA to 300-mA Peak Sink Current

• Integrated Gate Driver Power Supplies

– High-Side Charge Pump

– Low-Side Linear Regulator

• 6 to 38-V Operating Voltage Range

– 40-V Absolute Maximum Rating

• Integrated Commutation from Hall Sensors

– 120° Trapezoidal Current Control

– Low-Cost Hall Elements Input

– Tacho Output Signal (FGOUT) for Closed Loop Speed Control

• Cycle-by-Cycle Current Limit

• Supports 1.8-V, 3.3-V, and 5-V Logic Inputs

• Low-Power Sleep Mode

• Linear Voltage Regulator, 3.3 V, 30 mA

• Compact VQFN Package and Footprint

– 4-mm × 4-mm, 32-Pin VQFN Package

• Integrated Protection Features

– VM Undervoltage Lockout (UVLO)

– Charge Pump Undervoltage (CPUV)

– MOSFET Overcurrent Protection (OCP)

– Gate Driver Fault (GDF)

– Thermal Shutdown (OTSD)

– Fault Condition Indicator (nFAULT)

2 Applications

• BLDC Motor Modules

• Service Robots and Service Robotics

• Vacuum Cleaners

• Drones, Robotics, and RC Toys

• White Goods

• ATM and Currency Counting

3 Description

The DRV8306 device is an integrated gate driver for three-phase applications. The device provides three half-bridge gate drivers, each capable of driving highside and low-side N-channel power MOSFETs. The DRV8306 device generates the proper gate drive voltages using an integrated charge pump for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The smart gate drive architecture supports up to 150-mA source and 300-mA sink peak gate drive current and 15-mA rms gate drive current capability.

The device provides an internal 120° commutation for the trapezoidal BLDC motor. The DRV8306 device has three Hall comparators which use the input from the Hall elements for internal commutation. The duty ratio of the phase voltage of the motor can be adjusted through the PWM pin. Additional brake (BRK) and direction (DIR) pins are provided for braking and setting the direction of the BLDC motor. A 3.3-V, 30-mA low-dropout (LDO) regulator is provided to supply the external controller and Hall elements. An additional FGOUT signal is provided which is a measure of the commutation frequency. This signal can be used for implementing the closedloop control of BLDC motor.

A low-power sleep mode is provided to achieve low quiescent current draw by shutting down most of the internal circuitry. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin.

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