UCC27527

• Industry-Standard Pin Out
• Two Independent Gate-Drive Channels
• 5-A Peak Source and Sink Drive Current
• CMOS Input Logic Threshold (Function of
  Supply Voltage on VDD Pins)
• Hysteretic Logic Thresholds for High Noise
  Immunity
• Independent Enable Function for Each Output
• Inputs and Enable Pin Voltage Levels Not
  Restricted by VDD Pin Bias Supply Voltage
• 4.5-V to 18-V Single Supply Range
• Outputs Held Low During VDD UVLO (Ensures
  Glitch-Free Operation at Power Up and Power
  Down)
• Fast Propagation Delays (17-ns Typical)
• Fast Rise and Fall Times (7-ns and 6-ns Typical)
• 1-ns Typical Delay Matching Between 2 Channels
• Outputs Held in Low When Inputs Floating
• SOIC-8, and 3-mm × 3-mm WSON-8 Package Options
• Operating Temperature Range of –40°C to 140°C
• –5-V Negative Voltage Handling Capability on Input Pins

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