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Is the drain d and source s of the p-channel MOS in the figure reversed?

Hardware design
九月 29, 2020 by Donte 1418

My understanding (replace the drain d with the source s): B_VCC is USB power supply and is 5V. When the DC interface is not inserted, PSELF is grounded, then Ugs=-5V, PMOS is turned on, VCC=B_VCC; when the DC interface is inserted, PSELF is floating, S_VCC=5V, then Ugs=0, PMOS is turned off, VCC=S_VCC. In this way, the power supply can be switched.

I don’t know if it’s my understanding or the circuit?

PWE_select.png

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Giancarlo 发表于 September 29, 2020

This is no problem, but the body diode of the PMOS tube is borrowed. In this case, when there is no external power, the B_VCC will be powered by the body diode of the MOS tube. After the external power is connected, the PMOS tube will be closed under the influence of VGS, and the external voltage is greater than B_VCC-VF If the voltage is higher, external electricity will be used.

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Edison 发表于 September 29, 2020

Simulation test.

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Annette 发表于 September 29, 2020

What does the two VCC mean? A little dizzy.

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Stuart 发表于 September 29, 2020

DC is the main power and bat is the auxiliary power.

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